Embedded in Cork

Before examining the different key design areas relating to the PowerPC kernel implementation it’s worth taking a look at the overall system. The purpose of the kernel is to support a GSM radio platform capable of supporting two carriers of GSM, GPRS or EDGE. At the heart of the digital part of the radio is a PowerPC based communications processor (PowerQUICC 2). The other main digital components on the radio are illustrated in the diagram below and include digital signal processors (DSP), an ASIC, PCI bridge and memory.

The PowerPC based processor on the board is responsible for radio application software associated with initialization and control of the radio transceiver. This includes responsibility for configuring, monitoring and communicating with the DSP block. A number of software processes run on the processor to take care of the radio subsystem (needed for channel configuration, handover, power control etc.) a data link service provider for controlling a HDLC link off board and other maintenance applications for TTY debug and alarm monitoring.

The real time response of the platform comes from the timing demands of GSM. The PowerPC based kernel must provide real time response to multiple interrupt sources, including DSP interrupts at a frequency of 577 microseconds, GSM frame interrupts, sourced from the ASIC every 4.615 milliseconds, GSM Superframe interrupts every 6.12 seconds, HDLC interrupts and TTY interrupts.

With the above processing and interrupt handling requirements it’s clear that a real time operating system is needed. So why persist in porting or developing an in-house solution instead of going with an off the shelf option such as Linux or VxWorks? That’s a question I hope to tackle in the next article. Stay tuned….

PowerPC Kernel Implementation for GSM Radio Platform – Previous Posts

• PowerPC Kernel Implementation – Introduction

As part of my work with Motorola I had the opportunity to be part of a team that ported an RTOS (Real Time Operating System). The original RTOS ran on a Motorola/Freescale 68K (68000) series of processors and we moved it to a PowerPC based communications processor.

During the summer of 2007 I was able to co-present a paper about the work we did at the Embedded Systems and Applications conference of Worldcomp ‘07. The title of the paper is “PowerPC Kernel Implementation for GSM Radio Platform” and as it was published and presented in a public forum it gives me the liberty to openly discuss the contents of the paper on this blog.

My hope is that this will be the first of a series of posts that delves into the key areas involved in implementing a PowerPC kernel. The kernel is at the heart of the RTOS, managing context switching, memory, stack switching, interrupts and system calls. I hope to touch on all of those areas, with a focus on the optimisations introduced to minimise the impact of running with a fully enabled memory management unit and unique user/supervisor/interrupt stacks.